Program


  
8:15 AM 

8:30 AM 

Welcome Address and Opening Remarks 

 8:30 AM 
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9:30 AM

Keynote Address

David Mayhew, University of San Diego

SAHARA (Standard Architecture for Hardware Acceleration via Reconfigurable Arrays)

Faster, lower power, and/or less expensive computation will be a software problem forever more. Hardware can only make the software challenge simpler or harder. Heterogeneous and/or parallel architectural approaches only exacerbate the problem. Emerging alternative computational technologies like quantum, optical, resistive (and other forms of analog computation), and/or biological computing (among others) must be integrated into the existing computational infrastructure and in particular into the existing software infrastructure if they are to realize their full potential. The increasingly main-stream options that reconfigurable logic represents (both fine and coarse grained) will also be most useful within an infrastructure that is sympathetic to existing computation, particularly its memory and storage. SAHARA is a reduction of computation into data wave fronts that, independent of the underlying technology, employs memory as the fundamental unit of computation within a simple data-flow model, essentially turning processing into a side effect of the relevant data being made available to the logic that manipulates that data. No single aspect of SAHARA is “new”. Its foundations are more than 50 years old and centered on Minsky’s 1961 paper on Turing equivalence of minimal computational mechanisms, on Estrin and Viswanathan 1962 paper proposing the integration of fixed and variable logic, and on the plethora of single instruction architectures that emerged in the wake of Patterson’s RISC papers. SAHARA is an eminently useful abstraction of computation that has the potential of seamlessly integrating many disparate forms of computation behind a simple, common, architectural interface; and of allowing the underlying hardware technologies behind that standard interface to radically change without impacting peer system components.

Presentation

9:30 AM 
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10:00 AM 

Coffee break

10:00 AM 
12:00 AM

Technical Session

Sebastien Rumley, Robert P. Polster, Simon D. Hammond, Arun F. Rodrigues, Keren Bergman, End-to-end Modeling and Optimization of Power Consumption in HPC Interconnects

Presentation

Jiajun Wang, Ahmed Khawaja, George Biros, Andreas Gerstlauer, Lizy John, Optimizing GPGPU Kernel Summation for Performance and Energy Efficiency

Presentation

Moises Vinas, Basilio B. Fraguela, Diego Andrade, Ramon Doallo, Towards a High Level Approach for the Programming of Heterogeneous Clusters

Presentation

Borui Wang, Martin Torres, Dong Li, Jishen Zhao, Florin Rusu, Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications

Presentation

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